Figure 7 indicates how the PCR is utilized by the decoder to recreate a remote version of the 27-MHz clock for every program. The encoder clocks power a continuously strolling binary counter, and the value of those counters are sampled periodically and located inside the header adaptation fields as the PCR. Every encoder produces packets having a unique PID. The decoder acknowledges the packets with the proper PID for the chosen program and ignores others. On the decoder, a VCO generates a nominal 27-MHz clock and this drives a nearby PCR counter. The local PCR is in comparison with the PCR from the packet header, and the difference is the PCR section errors. this mistake is filtered to manipulate the VCO that finally will carry the local PCR count number into step with the header PCRs. Substantial VCO filtering guarantees that jitter in PCR transmission does not modulate the clock. The discontinuity indicator will reset the nearby PCR be counted and, optionally, can be used to lessen the filtering to assist the device fast lock to the brand new timing.